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RHF1401
Rad-hard 14-bit 20Msps 85mW A/D converter
Features

SO-48 package
Ssingle +2.5V supply operation Low power: 85mW @ 20Msps High linearity: +/- 0.3 bit DNL SFDR = 90dB typ. SINAD = 73dB typ. @ Fs = 20Msps, Fin = 5MHz 2.5V/3.3V compatible digital I/O Switchable on/off built-in reference voltage Hermetic package Rad-hard: 300kRad(Si) TID Failure immune (SEFI) and latchup immune (SEL) up to 120 MeV-cm2/mg at 2.7V and 125C Qml-V qualification on-going, smd 5962-06260
1 48
Pin connections (top view)
Applications

Digital communication satellites Space data acquisition systems Aerospace instrumentation Nuclear and high-energy physics
24
25
Description
The RHF1401 is a 14-bit, 20MHz maximum sampling frequency analog-to-digital converter using pure (ELDRS-free) CMOS 0.25m technology combining high performance, radiation robustness and very low power consumption. The RHF1401 is based on a pipeline structure and digital error correction to provide excellent static linearity. Its very low internal noise permits to achieve more than 11.8 ENOB with a 2.2Vpp 5MHz input.
Specifically designed for optimizing power consumption, the RHF1401 only dissipates 85mW at 20Msps, while maintaining a high level of performance. It integrates a proprietary trackand-hold structure to ensure an effective resolution bandwidth of 70MHz. A voltage reference is integrated in the circuit to simplify the design and minimize external components. A tri-state capability is available on the outputs, to allow common bus sharing. A data-ready signal which is raised when the data is valid on the output can be used for synchronization purposes. The RHF1401 has an operating temperature range of -55C to +125C and is available in a small 48-pin hermetic SO-48 package.
October 2007
Rev 2
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Contents
RHF1401
Contents
1 2 3 4 5 6 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 8 Electrical characteristics (unchanged after 300kRad) . . . . . . . . . . . . . . 9 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 Analog input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1.1 7.1.2 Setting the analog input range and references . . . . . . . . . . . . . . . . . . . 15 Driving the analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2 7.3 7.4 7.5 7.6
Clock signal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power consumption optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Low sampling rate recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Digital inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PCB layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1 8.2 Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9 10 11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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RHF1401
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. RHF1401 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 S0-48 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Linearity vs. Fin, internal references, Fs = 20 MHz, Icca = 40 mA . . . . . . . . . . . . . . . . . . . . 12 Linearity vs. Fin, external references (REFP = 1 V), Fs = 20 MHz, Icca= 28 mA . . . . . . . . 12 Distortion vs. Fin, internal refs, Fs = 20 MHz, Icca = 40 mA . . . . . . . . . . . . . . . . . . . . . . . . . 12 Distortion vs. Fin, external ref, (REFP = 1 V) Fs = 20 MHz; Icca = 28 mA . . . . . . . . . . . . . 12 2nd & 3rd harmonics vs. Fin, internal refs, Fs = 20 MHz; Icca = 40 mA. . . . . . . . . . . . . . . . . 13 2nd & 3rd harmonics vs. Fin, external ref REFP=1 V, Fs=20MHz; Icca=28mA . . . . . . . . . . . 13 Single-tone 16K FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Single-tone 16K FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SFDR vs. input amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Static parameter: differential non linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Static parameter: integral non linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Linearity vs. REFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Distortion vs. REFP(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External reference setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Linearity vs. Fs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Distortion vs. Fs(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ADC input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Differential input configuration with transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AC-coupled differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Analog current consumption vs. Fs according to value of Rpol polarization resistances: internal references (for Fin < 10MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Impact of clock frequency on RHF1401 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CLK signal derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SO-48 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Block diagram
RHF1401
1
Block diagram
Figure 1. RHF1401 block diagram
VREFP REFMODE VIN INCM VINB stage 1 stage 2 stage n Reference circuit IPOL VREFM DFSB Sequencer-phase shifting CLK OEB VCCBE +2.5/3.3V GNDBE Digital data correction DR DO AVCC +2.5V AGND Buffers TO D13 OR DGND AVDD +2.5V
Timing
2
Pinout
Figure 2. S0-48 pin connections (top view)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
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RHF1401 Table 1.
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 OR D13(MSB) D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0(LSB) DR VCCBE GNDBE VCCBI
Pinout Pin descriptions
Description
Digital buffer ground Digital buffer ground Digital buffer power supply NC NC Out of range output Most significant bit output Digital output MSB Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output LSB Data ready output(1) Digital buffer power supply Digital buffer ground Digital buffer power supply
Name
GNDBI GNDBE VCCBE
Observations
0V 0V 2.5 V/3.3 V Non connected Non connected CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5V /3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) 2.5 V/3.3 V 0V 2.5 V
Pin
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Name
REFMODE OEB DFSB AVCC AVCC AGND IPOL VREFP VREFM AGND VIN AGND VINB AGND INCM AGND AVCC AVCC DVCC DVCC DGND CLK DGND DGND
Description
Ref. mode control input Output enable input Data format select input Analog power supply Analog power supply Analog ground Analog bias current input Top voltage reference
Observations
2.5 V/3.3 V CMOS input 2.5 V/3.3 V CMOS input 2.5 V/3.3 V CMOS input 2.5 V 2.5 V 0V
1V
Bottom voltage reference 0 V Analog ground Analog input Analog ground Inverted analog input Analog ground Input common mode Analog ground Analog power supply Analog power supply Digital power supply Digital power supply Digital ground Clock input Digital ground Digital ground 0V 1 Vpp 0V 1 Vpp 0V 0.5 V 0V 2.5 V 2.5 V 2.5 V 2.5 V 0V 2.5 V compatible CMOS input 0V 0V
1. See load considerations in Section 3: Timing.
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Timing
RHF1401
3
Timing
Table 2.
Symbol Fs Tck DC TC1 TC2 Tod Tpd Tdr Ton Toff TrD TfD
Timing characteristics
Parameter Sampling frequency(1) Sampling clock cycle Clock duty cycle Clock pulse width (high) Clock pulse width (low) Data output delay (fall of clock to data valid) (2) Data pipeline delay Data ready rising edge delay after data change Falling edge of OEB to digital output valid data Rising edge of OEB to digital output tri-state Data rising time Data falling time 10 pF load capacitance 10 pF load capacitance 10 pF load capacitance 5 8.5
(1)
Test conditions
Min 1.5 50
Typ
Max 20 667
Unit MHz ns % ns ns
Fs = 20 Msps
50 25 25 7.5 8.5 0.5 1 1 6 3 13 8.5
ns cycles cycles ns ns ns ns
1. See clock recommendations in Section 7.2: Clock signal requirements on page 19 2. See Figure 3 and discussion below.
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RHF1401 Figure 3. Timing diagram
N+5 N+4 N-1 N+3 N N+1 N+2 N+8 N+9 N+6 N+7
Timing
CLK
Tpd + Tod
Tdr
OEB Tod DATA OUT N-9 N-8 N-7 N-6 N-5 Toff N-4 N-3 Ton N-1 N
DR
HZ state
The input signal is sampled on the rising edge of the clock while digital outputs are synchronized on the falling edge of the clock.
Load considerations
The size of the internal output buffers limits the maximum load on the data output signals and Data Ready to 10pF equivalent load. In particular, the shape and amplitude of the Data Ready signal, toggling at the clock frequency can be weakened by a higher equivalent load. In applications that impose higher load conditions, it is recommended to use the falling edge of the master clock instead of the Data Ready signal. This is possible because the output transitions are internally synchronized with the falling edge of the clock. For implementation information, refer to Section 7.2: Clock signal requirements on page 19. An alternative is to re-buffer the DR signal externally to avoid any risk of modifying the clock signal.
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Absolute maximum ratings and operating conditions
RHF1401
4
Absolute maximum ratings and operating conditions
Table 3.
Symbol AVCC DVCC VCCBI VCCBE IDout Tstg Rthjc ESD
Absolute maximum ratings
Parameter Analog supply voltage(1) Digital supply voltage
(1) (1)
Values 0 to 3.3 0 to 3.3 0 to 3.3 0 to 3.6 -100 to 100 -65 to +150 22 2
Unit V V V V mA C C/W kV
Digital buffer supply voltage
Digital buffer supply voltage(1) Digital output current Storage temperature Junction - case thermal resistance Electrostatic discharge - HBM: human body model (2)
1. All voltage values, except differential voltage, are with respect to the network ground terminal. The magnitude of input and output voltages must never exceed -0.3 V or VCC+0.3 V. 2. Human body model: 100pF discharged through a 1.5k resistor between two pins of the device, done for all couples of pin combinations with other pins floating.
Table 4.
Symbol AVCC DVCC VCCBI VCCBE VREFP VREFM
Operating conditions
Parameter Analog supply voltage Digital supply voltage Digital internal buffer supply Digital output buffer supply Forced top voltage reference Bottom internal reference voltage Test conditions Min 2.3 2.3 2.3 2.3 0.5 0 Typ 2.5 2.5 2.5 2.5 1 0 Max 2.7 2.7 2.7 3.4 1.4 0.5 Unit V V V V V V
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RHF1401
Electrical characteristics (unchanged after 300kRad)
5
Electrical characteristics (unchanged after 300kRad)
Test conditions are the following (unless otherwise specified):

AVCC = DVCC = VCCB = 2.5 V Fs= 20 Msps Fin= 2 MHz Vin@ -1 dBSF VREFM = 0 V Tamb= 25 C Analog inputs
Parameter Test conditions Min Typ 2 8 Max Unit Vpp pF kOhms MHz
Table 5.
Symbol
VIN-VINB Full scale reference voltage VREFP= 1 V Cin Zin ERB Input capacitance Input impedance Effective resolution bandwidth(1)
Fs= 20 Msps
3.3 70
1. See Section 8: Definitions of specified parameters on page 24 for more information.
Table 6.
Symbol
Internal references
Parameter Test conditions REFMODE='0' internal reference on REFMODE='1' internal reference off REFMODE='0' REFMODE='0' REFMODE='0' Min Typ 30 7.5 0.84 0 0.44 Max Unit Ohm kOhm V V V
Rout
Output resistance of internal ref
VREFP VREFM VINCM
Top internal reference voltage Bottom internal ref. voltage Input common mode voltage
Table 7.
Symbol VREFP VREFM VINCM
External references
Parameter Forced top reference voltage Forced bottom ref. voltage Forced common mode voltage Test conditions REFMODE='1' REFMODE='1' REFMODE='1' Min 0.8 0 0.4 Typ Max 1.4 0.2 1 Unit V V V
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Electrical characteristics (unchanged after 300kRad) Table 8.
Symbol DNL INL
See Figure 14
RHF1401
Static accuracy
Parameter Differential non linearity(1) Integral non linearity Monotonicity and no missing codes
(2)
Test conditions Fs=1.5 Msps Fs=1.5 Msps
Min
Typ +/-0.3 +/-2
Max
Unit LSB LSB
Guaranteed
1. SeeFigure 13 and Section 8: Definitions of specified parameters on page 24 for more information. 2. See Figure 14 and Section 8: Definitions of specified parameters on page 24 for more information.
Table 9.
Symbol Clock input VIL VIH
Digital inputs and outputs
Parameter Test conditions Min Typ Max Unit
Logic "0" voltage Logic "1" voltage
DVCC = 2.5 V DVCC = 2.5 V
0 2.0
0
0.8 2.5
V V
Digital inputs VIL VIH Logic "0" voltage Logic "1" voltage VCCBE = 2.5 V VCCBE = 2.5 V 0 0.75 x VCCBE 0.25 x VCCBE VCCBE V V
Digital outputs VOL VOH IOZ CL Logic "0" voltage Logic "1" voltage High impedance leakage current Output load capacitance IOL = -1 mA IOH = 1 mA OEB set to VIH VCCBE -0.2 -15 15 15 0 0.2 V V A pF
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RHF1401 Table 10.
Symbol
Electrical characteristics (unchanged after 300kRad) Dynamic characteristics
Parameter(1) Test conditions Fin = 10 MHz, internal reference Fin = 10 MHz, VREFP =1 V Fin = 10 MHz, internal reference SNR Signal to noise ratio Fin= 10 MHz, VREFP = 1 V Fin= 10 MHz, internal reference THD Total harmonic distortion Fin= 10 MHz, VREFP = 1 V Signal to noise and distortion ratio Fin= 10 MHz, internal reference Fin= 10 MHz, VREFP = 1 V Fin= 10 MHz, internal reference ENOB Effective number of bits Fin= 10 MHz, VREFP = 1 V 11.7 -85 70 dB 71 11.5 bits 71.5 -86 dBc Min Typ -91 dBFS -89 70 dB Max Unit
SFDR
Spurious free dynamic range
SINAD
1. See Section 8: Definitions of specified parameters on page 24 for more information.
Higher values of SNR, SINAD and ENOB can be obtained by increasing the analog input full scale range. This is illustrated in Figure 11 on page 13, Figure 18, and Figure 19 on page 17 with VREFP= 1.25V, and also in Figure 15 and Figure 16 on page 16 with VREFP up to 1.4V.
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Typical performance characteristics
RHF1401
6
Typical performance characteristics
Because of its intrinsic high-speed low-power capabilities, most of the characterization measurements for the RHF1401 were done in the analog frequency range from 1MHz to 100MHz. An evaluation board designed to operate in this range, and including a transformer to generate on-board differential signals to input to the RHF1401 was used in characterization testing. This configuration is illustrated in Figure 21 on page 18. For best performance, the RHF1401 also requires a high enough sampling frequency or, in other terms, that the clock period is not too long, to avoid current leakage which would impact conversion accuracy. The recommended lowest sampling frequency is 1.5Msps. Note that under 1.2Msps, the RHF1401 performance is degraded. For more information on sampling frequency, see Section 7.2: Clock signal requirements, and Section 7.3: Power consumption optimization.
Figure 4.
80
Linearity vs. Fin, internal references, Fs = 20 MHz, Icca = 40 mA
12 11.9
Figure 5.
Linearity vs. Fin, external references (REFP = 1 V), Fs = 20 MHz, Icca= 28 mA
12 ENO 11.8 11.6 SINA 11.4 11.2 11 ENOB (Bits)
30
Dynamic parameters (dB)
80 Dynamic parameters (dB) 77 74 71 68 65 5 15 Fin (Mhz) 25
77 74 71 68 65 0 5 10 15 20 Fin (Mhz) 25 30
11.8 11.6 11.5
SNR SINAD
ENOB
11.4 11.3 11.2 11.1 11
ENOB (Bits)
11.7
SNR
Figure 6.
-70 -75
Distortion vs. Fin, internal refs, Fs = 20 MHz, Icca = 40 mA
Figure 7.
Distortion vs. Fin, external ref, (REFP = 1 V) Fs = 20 MHz; Icca = 28 mA
-70 -75
Distortion (dBc)
Distortion (dBc)
-80
THD
-80 -85 -90
THD
-85
SFDR
-90 -95 -100 0 5 10 15 Fin (Mhz) 20 25 30
SFDR
-95 -100 5 10 15 20 25 Fin (Mhz)
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RHF1401 2nd & 3rd harmonics vs. Fin, internal Figure 9. refs, Fs = 20 MHz; Icca = 40 mA
-60 -65
Typical performance characteristics 2nd & 3rd harmonics vs. Fin, external ref REFP=1 V, Fs=20MHz; Icca=28mA
Figure 8.
-60 -65 -70
Distortion (dB)
-75 -80 -85 -90 -95 -100 -105 -110 0 5 10 15 Fin (Mhz) 20 25 30
H3 H2
Distortion (dB)
-70 -75 -80
H 3
-85 -90 -95 -100 -105 -110 5 10 15 20 F (Mhz) in 25
H 2
30
Figure 10. Single-tone 16K FFT
0 -2 0
Power spectrum (dB)
-4 0 -6 0 -8 0 -1 0 0 -1 2 0 -1 4 0 -1 6 0 -1 8 0 0 5 10
F (M h z)
1. At Fs = 20 Msps, internal references, Fin = 5 MHz, Icca = 40 mA, Vin@-1 dBFS, SFDR = -89.3 dBc, THD = -84.5 dBc, SNR = 70.5 dB, SINAD = 70.3 dB, ENOB = 11.5 bits
Figure 11. Single-tone 16K FFT
20 0 -2 0
Power spectrum
-4 0 -6 0 -8 0 -1 0 0 -1 2 0 -1 4 0 -1 6 0
0 5 10
F (M h z)
1. At Fs=20 Msps, external references, Fin= 5 MHz, Icca = 40 mA, Vin@-1 dBFS, VREFP= 1.25V, SFDR = -87.5 dBc, THD = 85.4 dBc, SNR = 73.3 dB, SINAD = 73 dB, ENOB = 11.84 bits
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Typical performance characteristics Figure 12. SFDR vs. input amplitude
-20 -30
RHF1401
SFDR(dBc and dBFS)
-40 -50 -60 -70 -80 -90
SFDR(dBFS) SFDR(dBc)
-100 -110 -30
-25
-20
-15 SFSR(dB)
-10
-5
0
1. (Full scale = 2 x 0.86 V), Fs = 20 Msps, Fin = 5 MHz, Icca = 40 mA
Figure 13. Static parameter: differential non linearity p
0.4 0.3 0.2 0.1 NLD (q14bits) 0 0.1 0.2 0.3 0.4 0.5 0.6 0 3276.6 6553.2 9829.8 1.31 10
4
1.64 10
4
1. Fs = 1.5 Msps acquisition over 128 DC linear ramping input signals
Figure 14. Static parameter: integral non linearity
3 2.4 1.8 1.2 NLI (q14Bits) 0.6 0 0.6 1.2 1.8 2.4 3 0 3276.6 6553.2 9829.8
4 4
1.31 10
1.64 10
1. Fs = 1.5 Msps acquisition over 128 DC linear ramping input signals
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RHF1401
Application information
7
Application information
The RHF1401 is a high speed analog-to-digital converter based on a pipeline architecture and the ST 0.25m CMOS process in order to achieve the best performance in terms of linearity, power consumption and radiation hardness. The pipeline structure consists of 14 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. Each of the first 13 stages consists of an analog to digital converter, a digital to analog converter, a sample and hold and an amplifier with a gain of 2. A 1.5-bit conversion resolution is done at each stage. The last stage is a 2-bit flash ADC. Each resulting LSBMSB couple is then time-shifted to recover from the delay caused by conversion. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) couple for each stage. The corrected data is output through the digital buffers. Signal input is sampled on the rising edge of the clock while digital outputs are synchronized on the falling edge of the clock. The advantages of this converter reside in the combination of a SEFI-free pipeline architecture and advanced low-voltage CMOS technology. The highest dynamic performance is achieved while consumption remains at the lowest level.
7.1
7.1.1
Analog input configuration
Setting the analog input range and references
To optimize the high resolution and speed of the RHF1401, we strongly advise you to drive the analog input differentially. The half full-scale of RHF1401 is adjusted through the voltage values of VREFP and VREFM:
V IN - V INB = Full Scale = 2 ( V REFP - V REFM )
The differential analog input signal always has a common mode voltage of:
V IN + V INB V CM = --------------------------2
To select the references according to the constraints of your particular application, a control pin, REFMODE, allows you to switch from internal to external references.
Internal references, common mode:
When REFMODE is set to VIL level, the RHF1401 operates with its own reference voltage generated by its internal bandgap. If the VREFM pin is connected externally to the analog ground while VREFP is set to its internal voltage (0.86 V), the full scale of the ADC is 2 x 0.86 = 1.72V. In this case, VREFP, VREFM and INCM are low impedance outputs. The INCM pin (voltage generator 0.46 V) may be used to supply the common mode, CM, of the analog input signal.
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Application information
RHF1401
External references, common mode:
In applications that require a different full scale magnitude, it is possible to force the VREFP and VREFM pins from an external voltage reference device. In this configuration, the RHF1401 has better performance, as illustrated in Figure 15 and Figure 16. Setting REFMODE to VIH level will put the internal references in standby mode, turning VREFP, VREFM and INCM into high impedance inputs that have to be forced by external references. Figure 15. Linearity vs. REFP(1)
80 Dynamic parameters (dB) 77
ENOB
Figure 16. Distortion vs. REFP(1)
12.4 12.2
-70 -75
ENOB (Bits)
12
SINAD
Distortion (dBc)
-80 -85 -90 -95 -100 0.8 0.9 1 1.1 REFP (V) 1.2 1.3 1.4
SFDR THD
74 71 68 65 0.8 0.9 1
SNR
11.8 11.6 11.4 11.2 11
1.1 1.2 REFP (V)
1.3
1.4
1. Fin = 5 MHz; Fs = 20 Mhz; Icca = 26 mA; VINCM=0.45 V
Using the RHF1401 with an external voltage reference device yields optimum performance when configured as shown in Figure 17. Figure 17. External reference setting
"1" 1k 330pF 10nF 4.7F
REFMODE VCCA VIN VREFP
RHF1401
VINB
external reference
VREFM
Note:
In multi-channel applications, the high impedance input of the references allows you to drive several ADCs with only one voltage reference device. In the case of a 1.25V external reference, the full scale is increased to 2.5 Vpp differential. The improved dynamic performance is shown in Figure 18 and Figure 19.
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RHF1401 Figure 18. Linearity vs. Fs(1)
80 12.1 12 11.8 74 71 68 65 3 5 7 9 11 13 Fs (Mhz) 15 17 19 21
SNR SINAD ENOB
Application information Figure 19. Distortion vs. Fs(1)
-70 -75
Dynamic parameters (dB)
Distortion (dBc)
77
11.9 11.7 11.6 11.5 11.4 11.3 11.2 11.1
ENOB (Bits)
-80 -85
THD
-90 -95 -100 3 5 7 9
SFDR
11 13 Fs (Mhz)
15
17
19
21
1. At Fin = 5 MHz, using external REFP = 1.25 V, Icca optimized, VINCM = 0.65 V
The magnitude of the analog input common mode, CM should stay close to VREFP/2. Higher levels will introduce more distortion.
7.1.2
Driving the analog inputs
The RHF1401 is designed to be differentially driven for better noise immunity. Measurements done with single-ended signals show reduced levels of performance. The switch-capacitor input structure of RHF1401 has a high input impedance (3.3 k at FS = 20MHz) but it is not constant in time (see the equivalent input circuit in Figure 20) because, at the end of each conversion, the charge update of the sampling capacitor draws or injects a small transient current on the input signal. One method of masking this transient current is a low-pass RC filter as shown in Figure 21 and Figure 22. A capacitor with a higher value than the sampling capacitor of 2.4 pF, mounted in parallel with the two analog input signals, will absorb the transient glitches. Figure 20. ADC input equivalent circuit
AVcc
Switch at Fs VIN VIN Cs=2.4pF
AGND
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Application information
RHF1401
Single-ended signal with transformer
Using an RF transformer is an efficient method of achieving high performance. Figure 21 shows the schematic view. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. Figure 21. Differential input configuration with transformer
Analog source ADT1-1 1:1 VIN 50 100pF VINB INCM
RHF1401
330pF
10nF
4.7F
The internal common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46 V. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source.
AC coupled differential input:
Figure 22 represents the biasing of a differential input signal in AC-coupled differential input configuration. Both inputs VIN and VINB are centered around the common mode voltage CM, that can be forced through INCM or supplied externally (in this case, INCM may be left internal). Figure 22. AC-coupled differential input
50
10nF 100k 33pF INCM 100k 10nF
VIN
RHF1401
common mode
VINB
50
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RHF1401
Application information
7.2
Clock signal requirements
The signal applied to the CLK pin is critical to obtain full performance from the RHF1401. It is recommended to use a 0V to 2.5V square signal with fast transition times, and to place proper termination resistors as close as possible to the device. It is the rising edge of the clock signal that determines the sampling instant. The jitter associated with this instant must be as low as possible to avoid SNR degradation on fast moving input signals. To achieve less than 0.5 LSB error, the total jitter Tj must satisfy the following condition for a full scale input signal:
1 T j < -------------------------------------n+1 F in 2
For example, the total jitter with 14-bit resolution for a 10 MHz full scale input should be no more than 1 picosecond (rms). In most cases, it is the clock signal jitter that is the major contributor to the total jitter. Therefore, you must pay particular attention to the clock signal in the case of acquisition of fast signals with a low frequency clock. For further considerations on low sampling conditions, refer to Section 7.4 on page 20. The clock signal must be active when you power up the device. Clock gating (stopping the clock) is not recommended due to possible undertermined states inside the circuit when the clock is off.
7.3
Power consumption optimization
The internal architecture of the RHF1401 makes it possible for you to optimize the analog power consumption depending on the sampling frequency by adjusting the Rpol resistor. This resistor is placed between the IPOL pin and the analog ground.
Input signal below 10MHz
Depending of the application sampling speed, the Rpol value should be set between 120 k (low sampling speed, low current) and 40 k (high sampling speed, high current). With a low sampling speed, you should use a high value for Rpol (for example 100 k) in order to minimize the power consumption, often critical in space applications. This method is efficient with an input signal in the range from DC up to 10MHz. With a sampling frequency of 20 MHz, an Rpol value of 41 k provides optimized power consumption. Figure 23 shows the optimized power consumption of the circuit versus the sampling frequency in two different configurations:

REFMODE=0 internal references with IAVCC in the range 30-40 mA REFMODE=1 external references with IAVCC in the range 20-30 mA
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Application information
RHF1401
Figure 23. Analog current consumption vs. Fs according to value of Rpol polarization resistances: internal references (for Fin < 10MHz)
45 140 120 40 Rpol
REFMODE= 0 Ipol_intref
I(Avcc)(mA) 35
100 80 60 40 Rpol (kOhm)
30
25
REFMODE= 1 Ipol_extref
20 0
20 5 7 9 11 13 Fs (Mhz) 15 17 19 21
Input signal above 10MHz
However, with a higher frequency input signal (for example, in the 10-70MHz range), a high Rpol value does not supply enough current to the internal amplifiers, thus resulting in degraded SNR and THD performance. With an input signal in this range, the recommended value for Rpol is in the 30-50 k range.
7.4
Low sampling rate recommendations
The RHF1401 offers a wide range of sampling rates from 1.5Msps to 20Msps with the minimum power consumption. However, under the minimum, the performance of the device deteriorates. Figure 24 shows the degradation in performance at sampling frequencies under 1.2Msps. The recommended minimum sampling frequency is 1.5Msps.
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RHF1401
Application information Figure 24. Impact of clock frequency on RHF1401 performance
80 70 60 50 SNR 40 30 20 10 0 1 5 Fin 15 25 Fs = 1.0 Msps Fs = 1.2 Msps Fs = 1.5 Msps
In the case of under-sampling, that is when the sampling rate is much lower than the input signal frequency (for example a 2Msps sampling rate with a 41.3MHz input signal), there are two critical parameters to consider:

The value of the Rpol resistor The clock jitter
7.5
Digital inputs/outputs
Data format select (DFSB)
When set to low level (VIL), the digital input DFSB provides a two's complement digital output MSB. This can be of interest when performing further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding.
Output enable (OEB)
When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital output buffers are in high impedance state. It results in lower consumption while the converter goes on sampling. When OEB is set to low level again, the data is then delivered on the output with a very short Ton delay.
Out of range (OR)
This function is implemented on the output stage in order to set up an "Out of range" flag whenever the digital data is over the full scale range. Typically, there is a detection of all the data at '0' or all the data at '1'. This ends up with an output signal OR which is in low level state (VOL) when the data is within the range, or in high level state (VOH) when the data is out of the range.
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Application information
RHF1401
Data ready (DR)
The data ready output signal is an image of the clock being synchronized on the output data (D0 to D13). This is a very helpful signal that simplifies the synchronization of the measurement equipment or the controlling DSP. As all other digital outputs, DR goes into high impedance state when OEB reaches high level as described in Figure 3: Timing diagram on page 7. Caution: Because the driving force of data outputs and the DR signal is relatively low, it is recommended to limit the equivalent load on these signals to 10-15pF maximum. This is to avoid a weak signal when the RHF1401 is clocked at full speed (20Msps). The DR signal is potentially the most affected because it has the highest frequency (20MHz maximum). If the equivalent load on the data outputs is slightly higher than 15pF, you can avoid resorting to external re-buffering of the data bus and DR signal by connecting the data bus to the acquisition device directly without using the DR. In this case, you can obtain a good validation signal from a derivation of the clock because the clock falling edge is used by the RHF1401 internally to generate data output transitions. A series resistor of approximately 100-200 Ohms should be placed at the derivation to avoid the effect of current spikes on the critical CLK node. This configuration is illustrated in Figure 25. Figure 25. CLK signal derivation
D0-D13
CLK 50
DR
ASIC or FPGA
100-200
above 15pF
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RHF1401
Application information
7.6
PCB layout precautions
To use the ADC circuits most efficiently at high frequencies, some precautions have to be taken for power supplies:
First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low-inductance and low-resistance common return. The separation of the analog signal from the digital part and from the buffers power supply is essential to prevent noise from coupling onto the input signal. Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. Proper termination of all inputs and outputs is needed; with output termination resistors, the amplifier load is resistive only and the stability of the amplifier is improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, use buffers or latches close to the output pins. It is also helpful to use 47 to 56 series resistors at the ADC output pins, located as close to the ADC output pins as possible. Choose component sizes as small as possible (SMD).

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Definitions of specified parameters
RHF1401
8
8.1
Definitions of specified parameters
Static parameters
Static measurements are performed using the histograms method on a 2 MHz input signal, sampled at 50 Msps, which is high enough to fully characterize the test frequency response. The input level is +1 dBFS to saturate the signal.
Differential non linearity (DNL)
The average deviation of any output code width from the ideal code width of 1LSB.
Integral non linearity (INL)
An ideal converter exhibits a transfer function which is a straight line from the starting code to the ending code. The INL is the deviation from this ideal line for each transition.
8.2
Dynamic parameters
Dynamic measurements are performed by spectral analysis, applied to an input sinewave of various frequencies and sampled at 50 Msps.
Spurious free dynamic range (SFDR)
The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc.
Total harmonic distortion (THD)
The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB.
Signal to noise ratio (SNR)
The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (Fs/ 2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB.
Signal to noise and distortion ratio (SINAD)
A similar ratio to the SNR but including the harmonic distortion components in the noise figure (not the DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 x ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD= 6.02 x ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits.
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RHF1401
Definitions of specified parameters
Analog input bandwidth
The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3 dB. Higher values can be achieved with smaller input levels.
Pipeline delay
Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles.
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Package information
RHF1401
9
Package information
Figure 26. SO-48 package mechanical drawing
Table 11.
SO-48 package mechanical data
Dimensions
Ref. Min. A b c D E E1 E2 E3 e f L P Q S1 12.28 1.30 0.66 0.25 6.22 1.52 2.18 0.20 0.12 15.57 9.52
Millimeters Typ. 2.47 0.254 0.15 15.75 9.65 10.90 6.35 1.65 0.635 0.20 12.58 1.45 0.79 0.43 12.88 1.60 0.92 0.61 0.483 0.051 0.026 0.010 6.48 1.78 0.245 0.060 Max. 2.72 0.30 0.18 15.92 9.78 Min. 0.086 0.008 0.005 0.613 0.375
Inches Typ. 0.097 0.010 0.006 0.620 0.380 0.429 0.250 0.065 0.025 0.008 0.495 0.057 0.031 0.017 0.507 0.063 0.036 0.024 0.255 0.070 Max. 0.107 0.012 0.007 0.627 0.385
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RHF1401
Ordering information
10
Ordering information
Table 12. Order codes
Temperature range Package Marking RHF1401KSO1 -55 C to 125 C SO-48 RHF1401KSO2 F0626001VXC
Part number RHF1401KSO1 RHF1401KSO2 RHF1401KSO-01V
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Revision history
RHF1401
11
Revision history
Table 13.
Date
Document revision history
Revision Changes First public release. Failure immune and latchup immune value increased to
29-Jun-2007
1
120 MeV-cm2/mg.
Updated package mechanical information. Removed reference to non rad-hard components from External references, common mode: on page 16. Updated Figure 1: RHF1401 block diagram. Added explanation on Figure 3: Timing diagram. Added introduction to Section 6: Typical performance characteristics. Updated Section 7.2: Clock signal requirements and Section 7.3: Power consumption optimization. Added Section 7.4: Low sampling rate recommendations. Updated information on Data Ready signal in Section 7.5: Digital inputs/outputs. Added Figure 24: Impact of clock frequency on RHF1401 performance and Figure 25: CLK signal derivation.
29-Oct-2007
2
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RHF1401
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